India's most industry-aligned semiconductor training ecosystem. Train under chip design Experts with hands-on EDA lab access, real tapeout projects, and guaranteed placement support.
0Engineers Trained
0% Placement Rate
0Hiring Partners
0Years Industry Exp.
SEMICON7nmVLSI DESIGN
RTL Design
SystemVerilog
Floorplan
STA
UVM
DRC/LVS
RTL Design
Verilog / SystemVerilog
UVM Verification
Floorplanning
Static Timing Analysis
Physical Design
GDSII Signoff
DRC / LVS
Cadence Genus
Synopsys ICC2
Primetime STA
Mentor Calibre
Clock Tree Synthesis
IR Drop Analysis
RTL Design
Verilog / SystemVerilog
UVM Verification
Floorplanning
Static Timing Analysis
Physical Design
GDSII Signoff
DRC / LVS
Cadence Genus
Synopsys ICC2
Primetime STA
Mentor Calibre
Clock Tree Synthesis
IR Drop Analysis
// INDUSTRY OPPORTUNITY
Why VLSI is India's Biggest Tech Opportunity
India's semiconductor design sector is poised for exponential growth. Over 20% of global chip design work already happens in India โ and the demand is only accelerating.
$150BGlobal Semiconductor Market by 2030
85K+VLSI Engineers Needed in India (2025-28)
โน18 LPAAverage Starting Package (VLSI)
300+Semiconductor Design Centers in India
40%YoY Growth in VLSI Job Postings
// PROGRAMS
Industry-Aligned VLSI Programs
โก
// VLSI FRONT-END
RTL Design & Functional Verification
From specification to simulation. Master RTL design, advanced SystemVerilog, UVM methodology, and functional coverage for complex SoC designs.
VerilogSystemVerilogUVMAssertionsCDC/RDC
๐ 6โ8 Months๐ Beginner โ Expert
๐ง
// VLSI BACK-END
Physical Design & Implementation
RTL to GDSII mastery. Floorplanning, placement, CTS, routing, STA, and full physical verification flow for production-grade chip delivery.
FloorplanCTSSTADRC/LVSIR Drop
๐ 6โ8 Months๐ Intermediate โ Expert
๐งฉ
// SYSTEM MODELLING
SystemC, RISC-V Architecture & GPUs
Model and simulate complex hardware systems at transaction level. Master SystemC TLM-2.0, RISC-V ISA, GPU architecture, and high-level system design used in pre-silicon verification and architecture exploration.
SystemCTLM-2.0RISC-VGPU ArchitectureESL Design
๐ 4โ6 Months๐ Intermediate โ Expert
๐ฅ๏ธ
// EDA LABS
Hands-On EDA Lab Access
Industry-standard EDA tools from Cadence, Synopsys, and Siemens. Remote cloud lab access, real project tapeouts, and guided lab sessions.
CadenceSynopsysSiemens EDALinux
๐ฌ Real EDA Toolsโ๏ธ Remote Access
💻
// SCRIPTING & AUTOMATION
Linux, Perl, TCL/TK & EDA Automation
Master the scripting backbone of every semiconductor company. Linux workflows, Shell & Perl automation, TCL for EDA tools, TCL/TK GUIs -- the skills every VLSI engineer uses daily.
LinuxShellPerlTCL / TKEDA Automation
📅 3-4 Months🎓 Beginner to Expert
// CHIP DESIGN JOURNEY
The Complete Chip Design Flow
You'll learn every stage of the silicon design pipeline โ from specification to GDSII tapeout.
Specification
โ
RTL Design
โ
Simulation
โ
Synthesis
โ
Floorplan
โ
Placement
โ
CTS
โ
Routing
โ
Signoff
โ
GDSII ๐
// WHY SEMICON GURUKUL
Engineered for Real Industry Success
๐ญ
Industry Experts as Mentors
Learn from engineers with 10โ20 years in leading semiconductor companies across India, US, and Europe.
๐ฌ
Real EDA Tool Access
Hands-on access to industry-standard Cadence, Synopsys, and Siemens EDA toolchains โ not toy simulators.
๐
Live Tapeout Projects
Work on real chip projects. Your portfolio includes verified RTL and physical design deliverables recruiters value.
๐ฏ
Placement-First Approach
Dedicated placement cell, mock interviews, resume reviews, and direct access to 48+ hiring semiconductor companies.
๐ก
Remote Lab Access
24/7 cloud-based EDA lab access from anywhere in India. No need to relocate โ learn from your city.
๐
Industry-Recognized Certificate
Completion certificates backed by our industry partners, recognized at Tier-1 semiconductor companies nationwide.
// SUCCESS STORIES
Engineers Who Made It to Silicon Valley
โ โ โ โ โ
"
Semicon Gurukul's UVM methodology training is unlike anything I found online. The structured mentorship and real EDA lab access got me confident enough to crack a top-tier verification interview in just 5 months.
RK
Rahul Kumar
Verification Engineer | B.Tech ECE, NIT Jaipur
โ Placed at Qualcomm India
โ โ โ โ โ
"
Physical design was a black box to me before Semicon Gurukul. The step-by-step floorplan to signoff flow, combined with Synopsys ICC2 training, made me industry-ready. The placement team was phenomenal.
Coming from a software background, I was skeptical. But the Front-End RTL course was designed so systematically that within 7 months I was writing production-grade SystemVerilog. Best investment of my career.
Get weekly insights on VLSI career trends, EDA tool updates, and exclusive workshop invites.
// FAQ
Frequently Asked Questions
Who is this training suitable for? +
Our programs are designed for B.Tech / M.Tech / B.E. graduates in ECE, EEE, EE, and CS. We also accept students who are in their final year. Some advanced modules require basic electronics and digital logic background, but we offer a digital foundations bootcamp for those who need it.
Do I need prior VLSI knowledge? +
No! Our Front-End program starts from absolute basics โ Verilog syntax, digital design fundamentals โ before advancing to SystemVerilog and UVM. For Back-End, basic CMOS knowledge helps but is not mandatory. We provide pre-course preparation material for all enrolled students.
What EDA tools will I get access to? +
Enrolled students get cloud-based access to industry-standard EDA tools including Cadence Xcelium for simulation, Synopsys VCS, Cadence Genus for synthesis, Synopsys ICC2 for physical design, and Cadence Tempus / Synopsys Primetime for STA. Linux environment access is provided 24/7.
What is the expected salary after placement? +
Our placed students typically receive offers between โน6 LPA to โน22 LPA depending on prior experience, company, and role. Freshers with strong RTL/PD skills average โน8โ12 LPA. With 2 years of relevant work (internship + training) some students have received โน18โ22 LPA offers.
Are classes online or offline? +
We offer both modes. Live online classes with recorded sessions for flexibility, or offline batches at our Bengaluru center. Hybrid mode is also available. All students regardless of mode get the same EDA lab access and placement support.
Is there an EMI or installment payment option? +
Yes, we offer 0% interest EMI options through partnered NBFCs and direct installment plans for up to 6 months. Contact our admissions team for personalized fee structure details.
Do you provide placement guarantee or assistance? +
We provide 100% placement assistance. We have active tie-ups with top tier semiconductor product companies and ASIC design service firms. Our placement cell also helps with resume building, soft skills, and conducts multiple mock technical interviews to make you industry-ready.
What is the duration of the training programs? +
Our comprehensive programsโsuch as Advanced ASIC Verification and Physical Designโtypically span 4 to 6 months. This timeline includes intensive theory sessions, exhaustive daily labs, mini-projects, and a final industry-standard major project.
Will I get to work on real-time industry projects? +
Absolutely. Practical exposure is the core of our curriculum. Front-end students verify standard protocols like AMBA APB/AHB, AXI, I2C, or SPI. Back-end students work on sub-7nm technology nodes handling complex macro blocks from floorplanning to final tape-out sign-off.
Who are the trainers for these programs? +
All our instructors are working professionals and industry veterans with 8 to 15+ years of experience in top semiconductor companies. This ensures that you are learning current, practical methodologies rather than just academic theories.
Which should I choose: Front-End (Verification) or Back-End (Physical Design)? +
It depends on your interests! If you enjoy coding, logic puzzles, and finding bugs, Front-End (RTL Design/Verification) is a great fit. If you prefer visual problem-solving, electronics physics, handling constraints, and layout optimizations, Back-End (Physical Design/STA) is the way to go. We offer free career counseling sessions if you are unsure.
Do I receive a certificate upon completion? +
Yes, upon successful completion of the coursework, passing the internal assessments, and finishing your major project, you will receive an industry-recognized certification that adds significant value to your resume.
// VLSI FRONT-END TRACK
RTL Design & Functional Verification
From digital logic to silicon-ready RTL. Master Verilog, SystemVerilog, UVM, and everything in between with real chip project experience.
Model real hardware before silicon. Master Electronic System-Level (ESL) design using SystemC TLM-2.0, explore RISC-V ISA from scratch, and understand modern GPU micro-architecture โ skills used daily by system architects at top semiconductor companies.
// SYSTEM DESIGN FLOW
From Architecture to Silicon
Architecture Spec
โ
SystemC Model
โ
TLM-2.0 Simulation
โ
RISC-V ISS
โ
GPU Micro-arch
โ
RTL Handoff โ
// THREE PILLARS
What You'll Master
โ๏ธ
// PILLAR 1
SystemC & TLM-2.0
Model hardware at transaction level before RTL. Build cycle-accurate and loosely-timed models, interconnects, memory systems, and full SoC platform prototypes using industry-standard SystemC TLM-2.0.
Understand the open RISC-V ISA from base integer instructions to extensions. Build a cycle-accurate instruction set simulator (ISS) in SystemC, implement pipeline stages, and explore custom extensions.
RV32I / RV64IM / F / D ExtPipeline DesignHazard HandlingCustom Extensions
๐ฎ
// PILLAR 3
GPU Architecture
Explore modern GPU micro-architecture: SIMT execution, warp scheduling, memory hierarchy, cache coherence, and compute pipelines. Model a simplified GPU core in SystemC and analyze performance bottlenecks.
Mastering SystemC data types, bit-level modelling, hardware concurrency through delta cycles, and inter-process synchronization using events and mutexes.
Build loosely-timed and approximately-timed models of buses, memories, and interconnects using the IEEE TLM-2.0 standard โ the backbone of virtual platform development.
tlm_initiator_sockettlm_target_sockettlm_generic_payloadb_transport (blocking)nb_transport_fw / nb_transport_bwLoosely-Timed (LT) coding styleApproximately-Timed (AT) coding styletlm_quantumkeeperSimple bus / router modelMemory model (read/write backdoor)DMI (Direct Memory Interface)Debug transport interface
Integrate processor model, memory, peripheral IPs, and interrupt controller into a complete virtual platform. Run bare-metal software on the platform before RTL exists.
Processor stub modelAHB/AXI bus fabric in TLMMemory map & address decodingPeripheral IP models (UART, SPI, GPIO)Interrupt controller modelDMA modelBare-metal software executionPerformance estimationPower annotations
05
Module 05 ยท Weeks 14โ17 ยท RISC-V ISA & ISS
RISC-V Architecture: ISA, Pipeline & ISS
Deep dive into the RISC-V open ISA. Understand instruction encoding, privilege levels, exception handling, and build a functional instruction set simulator (ISS) in SystemC/C++.
RV32I base integer ISARV64I extensionsM extension (mul/div)F / D extensions (floating point)C extension (compressed)A extension (atomics)Instruction encoding formats (R/I/S/B/U/J)Fetch โ Decode โ Execute โ Mem โ WBHazard detection (data/control)Branch predictionPrivilege levels (M/S/U mode)Exception & interrupt handling (MTVEC, MEPC)CSR registers (mstatus, mie, mip)RISC-V ISS in SystemC
Extend the base RISC-V ISA with custom instructions, integrate the processor with a memory subsystem and peripherals, and explore RISC-V SoC design patterns used in industry.
Custom opcode space (custom-0..3)RISC-V toolchain (GCC, objdump)Linker scripts & startup codeMemory-mapped I/O in RISC-VCLINT / PLIC controllersMulti-core RISC-V (SMP basics)TileLink / AXI-lite interfaceRISC-V SoC in SystemC TLM
07
Module 07 ยท Weeks 21โ24 ยท GPU Architecture
GPU Micro-Architecture: SIMT, Warps & Memory
Understand the architecture of modern GPUs from the streaming multiprocessor (SM) level down to individual execution units. Explore SIMT execution, thread hierarchy, and the memory subsystem.
GPU vs CPU architecture philosophyThread / Warp / Block / Grid hierarchySIMT (Single Instruction Multiple Thread) executionStreaming Multiprocessor (SM) internalsWarp scheduler (GTO / round-robin / two-level)Instruction issue & scoreboardingRegister file designShared memory & bank conflictsL1 / L2 cache hierarchyMemory coalescing rulesGlobal / shared / local / constant memoryTexture cache & special function units (SFU)Compute pipeline (ALU, FP32, FP64, INT, tensor)Occupancy & resource partitioning
Model a simplified GPU compute core in SystemC TLM. Simulate kernel execution, analyze memory access patterns, and instrument performance counters โ mirroring real GPU architecture simulation workflows.
Simplified SM model in SystemCWarp state machine (fetch/decode/issue/execute)Instruction dispatch queueOperand collectorMemory subsystem model (L1 + shared)Interconnect model (crossbar)Performance counters (IPC, occupancy, bandwidth)Bottleneck analysis (compute-bound vs memory-bound)Kernel launch & grid simulation
09
Module 09 ยท Weeks 29โ32 ยท Capstone Project
Capstone: RISC-V + GPU Heterogeneous SoC in SystemC
Build a complete heterogeneous SoC model: RISC-V host processor connected to a simplified GPU accelerator over TLM-2.0 AXI fabric, with DMA, shared memory, and software-driven kernel dispatch.
Skills That Put You in the Top 1% of VLSI Engineers
๐๏ธ
Pre-Silicon System Modelling
SystemC virtual platforms are used to develop firmware and software months before RTL tapeout. This is a critical skill at ARM, Intel, Qualcomm, and NVIDIA.
๐ฒ
RISC-V Is the Future
Open, extensible, and royalty-free โ RISC-V is adopted by Google, NVIDIA, Western Digital, and India's semiconductor mission. Deep ISA knowledge is in high demand.
๐ฎ
GPU Architecture Is Booming
AI/ML acceleration has made GPU architecture knowledge one of the most sought-after skills. Understanding SM design, memory hierarchy, and warp scheduling sets you apart.
๐ฌ
Architecture Exploration
Use SystemC models to evaluate design trade-offs (area vs performance vs power) before committing to RTL โ a workflow used in every major chip company's architecture team.
๐ค
Bridges HW & SW Worlds
SystemC and RISC-V knowledge lets you work at the intersection of hardware and software โ a rare and extremely valued skill in SoC companies.
๐
Industry-Ready Portfolio
Graduate with a complete RISC-V ISS, a GPU compute core model, and a heterogeneous SoC simulation โ a portfolio that speaks louder than any certificate.
// ENROLL NOW
Ready to Master System-Level Design?
Next batch starts soon. Limited seats available. Book your free demo session today.
// SCRIPTING & AUTOMATION TRACK
Linux ยท Shell ยท Perl ยท TCL/TK & EDA Automation
The scripting skills that separate a good VLSI engineer from a great one. Every semiconductor company runs on Linux automation, Perl parsers, and TCL-driven EDA tools โ learn them all from scratch to industry-ready.
// SKILL PROGRESSION
From Zero to EDA Automation Expert
Linux CLI
→
Shell Scripting
→
Perl Automation
→
TCL for EDA
→
TCL/TK GUI
→
Capstone Projects ✓
// COURSE PILLARS
Eight Modules, One Complete Skillset
🐧
// MODULES 1 & 7
Linux Fundamentals & Advanced Utilities
Master the semiconductor Linux environment โ file system, permissions, editors, grep/awk/sed pipelines, process management, remote access, and advanced multi-server batch computing.
Write regression launchers, simulation automation wrappers, and batch log analyzers in Shell. Then master Perl โ the backbone of EDA infrastructure โ for regex-based log parsing, timing report extraction, and UVM log analysis.
TCL is the primary scripting language inside every major EDA tool. Master TCL for Cadence Innovus, Tempus, and Genus. Then build real GUI dashboards and tool launchers using TCL/TK widgets.
Tie everything together โ build full automation frameworks for verification regression, STA analysis, physical design QoR reporting, and DRC tracking. Five industry-grade capstone projects you can show in interviews.
Perl powers regression infrastructure and EDA automation at every major chip company. Master it from basics to advanced regex-based timing report parsing.
Level up your Linux automation โ advanced awk/sed pipelines, distributed execution across server farms, Makefile-driven build flows, and Git-based team scripting.
awk advanced scriptingsed transformations & multi-file parsingDistributed execution & server farm handlingMakefile build automation & dependenciesGit version control basicsCollaborative scripting workflowsLab: Multi-server executionLab: Automated build flowLab: Git-based automation repository
08
Module 08 ยท Industrial Capstone Projects
5 Real Industry Projects โ Portfolio Ready
Apply everything in five complete industry-grade projects for your GitHub portfolio and interviews.
Launch 100s of UVM simulation jobs, collect results, parse logs, classify failures, and generate HTML summary reports -- all automatically.
⏱️
STA Violation Tracking
Extract setup/hold violations from Tempus reports, categorize by path groups, track across MCMM corners, and generate Excel-ready CSV summaries.
📐
Physical Design QoR
Parse Innovus congestion reports, DRC counts, and wire length metrics across iterations. Build dashboards that show PD closure progress at a glance.
📊
Coverage Analysis
Merge coverage databases, extract per-test contributions, identify uncovered bins, and drive targeted regression for faster closure.
💻
EDA GUI Tools
Build TCL/TK GUI launchers that let team members run complex EDA flows with a single button click -- no command-line expertise needed.
🧬
Synthesis Reporting
Automatically parse Genus reports, compare QoR across synthesis runs, and flag area/timing regressions in every nightly build.
// BONUS CONTENT
Bonus Modules Included
🐍
Python for VLSI Automation
Introduction to Python as a complement to Perl and TCL -- pandas for report parsing, matplotlib for QoR charts, and scripting EDA flows with Python subprocess.
pandasmatplotlibsubprocessCSV/Excel
🔄
Jenkins & CI/CD for Semiconductor
Set up Jenkins pipelines for nightly regression, automated tapeout checklists, and continuous integration of RTL/PD flows used at advanced semiconductor companies.
JenkinsCI/CD PipelineNightly RegressionAutomation
🤖
AI-Assisted Scripting
Use AI tools to accelerate TCL, Perl, and Shell script development -- prompt engineering for EDA automation, AI-driven log classification, and intelligent report parsing.
AI PromptingLog ClassificationCode GenerationProductivity
// ENROLL NOW
Ready to Automate the Chip Design World?
Next batch starts soon. Limited seats. Book your free demo session today.
// LABS & EDA TOOLS
Real EDA Lab Experience
No toy simulators. No university tools. You get access to the same EDA software used at Intel, Qualcomm, and TSMC โ from day one of training.
// CHIP DESIGN ECOSYSTEM
Complete EDA Tool Suite
Front-End Tools
Back-End Tools
Lab Infrastructure
๐ฎ
Cadence Xcelium
Simulation
๐
Synopsys VCS
Simulation
๐ญ
Verdi Debugger
Debug
๐
Questa Sim
Verification
๐
IMC Coverage
Coverage Merge
๐๏ธ
JasperGold
Formal Verify
๐
Vivado
FPGA Synthesis
๐
ModelSim
HDL Simulation
โ๏ธ
Cadence Genus
Synthesis
๐๏ธ
Cadence Innovus
Place & Route
๐ง
Synopsys DC
RTL Synthesis
๐
Synopsys ICC2
Physical Design
โฑ๏ธ
PrimeTime STA
Timing Signoff
โ
Calibre DRC/LVS
Physical Verify
โก
Apache RedHawk
Power Analysis
๐ก๏ธ
Cadence Tempus
Timing ECO
โ๏ธ
Cloud EDA Lab Access
Secure VPN-based remote access to high-performance Linux servers with pre-installed EDA toolchains. Available 24/7, 365 days a year.
๐ง
Linux Environment
Industry-standard RHEL / CentOS setup. Students master essential shell scripting, tcl automation, and Linux administration for EDA workflows.
๐ฅ๏ธ
High-Performance Servers
Multi-core compute clusters with 256GB+ RAM nodes for large-scale physical design runs and parallel regression testing.
๐
Project Repository
Git-based project management with code review. All your lab work, verification IPs, and PD implementations are portfolio-ready on day one.
๐
Enterprise-Grade Security
Secure VPN tunneling, user-based access control, and encrypted EDA license management. Your work stays yours.
๐น
Recorded Lab Sessions
Every lab session is recorded. Miss a session? Watch it back at 1x, 1.5x, or 2x. Lab recordings remain accessible for 12 months post-completion.
// PROJECTS
Real Chip Projects You'll Build
๐
// FRONT-END PROJECT
AXI4 Bus Controller Verification
Build a complete UVM testbench for an AXI4 master-slave protocol controller. Includes constrained random testing, functional coverage closure, and assertion-based verification.
UVMAXI4SVACoverage
๐งฎ
// FRONT-END PROJECT
RISC-V CPU Core RTL Design
Design and verify a 32-bit pipelined RISC-V RV32I processor core. Full pipeline stages: IF, ID, EX, MEM, WB with hazard detection and forwarding logic.
VerilogRISC-VPipelineSystemVerilog
๐ฆ
// BACK-END PROJECT
SoC Physical Design โ Full Flow
End-to-end physical implementation of a 32-bit SoC block: synthesis, floorplan, power plan, CTS, routing, STA closure, DRC/LVS clean GDSII tapeout.
ICC2InnovusPrimetimeCalibre
// CAREER & PLACEMENT
Your Path to a Semiconductor Career
94% of our students get placed within 3 months of completing the program. We don't just train engineers โ we launch careers.
94%Overall Placement Rate
โน18 LPAHighest Package Received
โน9.5 LPAAverage Starting Package
48+Active Hiring Partners
3 MonthsAverage Time to Placement
// CAREER PATHS
Roles You Can Target
๐ง
RTL Design Engineer
โน6L โ โน18L per annum
Design synthesizable RTL for ASICs and SoCs. Work on microarchitecture and block-level implementation in Verilog/SystemVerilog.
๐
Verification Engineer
โน7L โ โน22L per annum
Build and execute UVM testbenches for complex digital blocks. Coverage-driven verification with assertion-based checking.
๐
Physical Design Engineer
โน7L โ โน20L per annum
Own the floorplan to GDSII flow for ASIC blocks. Timing closure, power optimization, and signoff sign-off expertise.
โฑ๏ธ
STA Engineer
โน8L โ โน20L per annum
Perform static timing analysis across corners. Identify and fix setup/hold violations, manage multicycle paths and false paths.
๐ก๏ธ
DFT Engineer
โน7L โ โน18L per annum
Design-for-test insertion: scan chains, BIST, JTAG boundary scan, ATPG patterns, and test coverage optimization.
โ
Physical Verification Engineer
โน6L โ โน16L per annum
DRC/LVS clean signoff using Calibre and IC Validator. Waive or fix violations for foundry-ready GDSII submission.
โก
Power Integrity Engineer
โน8L โ โน20L per annum
IR drop, electromigration (EM) analysis and fixing, power planning optimization, and dynamic power simulation.
๐
Emulation / FPGA Engineer
โน7L โ โน18L per annum
FPGA-based SoC prototyping for pre-silicon validation. Work with Palladium/Zebu emulation platforms for system-level testing.
// PLACEMENT SUPPORT
Our Placement Machine
๐
VLSI Resume Building
Dedicated resume workshops by industry hiring managers. Your resume will speak the language semiconductor recruiters love.
๐ค
Mock Technical Interviews
Bi-weekly mock interviews simulating real Qualcomm, Intel, and MediaTek interview formats. Detailed feedback every session.
๐ค
Direct Referrals
Our alumni network and industry contacts provide direct referrals into top semiconductor design centers across India.
๐
Interview Question Bank
1000+ VLSI interview questions across RTL, verification, physical design, STA, and behavioral rounds โ updated monthly.
๐ผ
Company-Specific Prep
Tailored prep for each target company's interview style: Qualcomm, TI, Intel, Samsung, Broadcom, and more.
๐
LinkedIn & Portfolio Optimization
Professional LinkedIn review, GitHub project portfolio curation, and personal branding guidance for semiconductor engineers.
// HIRING PARTNERS
Where Our Engineers Land
Qualcomm India
Intel India
Texas Instruments
MediaTek India
Samsung Semiconductor
NXP Semiconductors
Broadcom India
Marvell Technology
ARM India
Microchip Technology
Renesas Electronics
Cadence Design
Synopsys India
Wipro VLSI CoE
Tata Elxsi
HCL Semiconductor
// SUCCESS STORIES
Placed Engineers Speak
โ โ โ โ โ
"
The placement team at Semicon Gurukul worked tirelessly. Within 2 weeks of finishing the UVM module, I had 4 interview calls. I cracked 2 of them. The company-specific prep is the real differentiator.
VN
Vikram Nair
Verification Engineer | Kerala โ Bangalore
โ Placed at NXP Semiconductors
โ โ โ โ โ
"
I was a mechanical engineer who pivoted to VLSI. Semicon Gurukul's structured curriculum and placement support made a seemingly impossible transition completely achievable. Got an offer at โน14 LPA.
The mock interviews were identical to my actual Qualcomm interview. I walked in prepared and confident. The STA + IR Drop training was extremely detailed โ exactly what they asked on day one of the interview.
SA
Shreya Agrawal
STA Engineer | M.Tech VLSI, IIT Bombay
โ Placed at Qualcomm India
// ABOUT US
Engineering India's Semiconductor Future
We are not a coaching institute. We are a semiconductor engineering academy built by industry Experts โ for the next generation of chip designers.
// OUR STORY
Why We Built This
Semicon Gurukul was founded by a team of VLSI engineers with decades of combined experience at global semiconductor companies. We saw a glaring gap: India produces tens of thousands of ECE graduates every year, yet the industry struggles to find job-ready chip designers.
The problem wasn't student potential โ it was the quality of training. Most institutes teach outdated tools, theoretical concepts without practical labs, and have zero connection to actual hiring companies.
We built Semicon Gurukul to fix that. Our curriculum is written by working engineers. Our labs use real EDA tools. Our placement cell has direct lines into HR and technical hiring managers at 48+ semiconductor companies across India.
"Every student who walks out of Semicon Gurukul should be productive from day one at any top chip company. That is our standard." โ Founder, Semicon Gurukul
๐ฏ
Industry-First Curriculum
Written by engineers currently working in the semiconductor industry.
๐ฌ
Hands-On First
Every concept is followed by immediate lab practice on real EDA tools.
๐ค
Mentorship Model
1-on-1 mentoring sessions, not just lectures. We invest in your success.
๐
Network Access
Tap into our 1200+ alumni network and industry placement connections.
// THE TEAM
Led by Industry Experts
Our faculty brings real-world semiconductor experience from global chip design centers. Not textbook professors โ practicing engineers.
AV
Arun Venkatesh
Lead Instructor โ Front-End VLSI
Former Senior Verification Engineer at Qualcomm India with 14 years of SoC verification experience. Specialist in UVM methodology, formal verification, and low-power design verification for mobile chipsets.
14 Yrs Industry Exp.UVM ExpertQualcomm Alumni
MK
Meenakshi Krishnan
Lead Instructor โ Back-End VLSI
Physical Design Lead with 11 years at MediaTek India and Samsung Semiconductor. Expert in advanced node (7nm/5nm) physical implementation, multi-voltage design, and IR/EM signoff for high-performance SoCs.
11 Yrs Industry Exp.Physical Design7nm/5nm Expert
RS
Rajendra Sharma
Placement & Career Lead
Former Technical Recruiter at Texas Instruments and NXP with 9 years of semiconductor talent acquisition experience. Knows exactly what hiring managers look for โ and trains students to deliver it.
covergroup declarationAutomatic & explicit samplingcoverpoint with auto-binsExplicit bins (ranges, values)ignore_bins / illegal_binsTransition bins (=>)Cross coveragebinsof() in cross ignoreoption.at_least / option.goalget_inst_coverage() / $get_coverage()Coverage-driven randomisation loopVerification plan to covergroup mapping
08
SV LAB 08 โ Packages & Parameterization
lab_packages_params.tar.gz
โถ
Package declaration & compilationimport pkg::* (wildcard)import pkg::name (explicit)Scope resolution (pkg::identifier)Package-level typedef/enum/structparameter with default valueslocalparam (non-overridable)Type parameters (#(type T))Parameterised class ScoreboardBase
09
SV LAB 09 โ Generate Blocks (Advanced)
lab_generate_blocks.tar.gz
โถ
generate for loopgenvar declarationNamed generate blocksHierarchical access to generate internalsgenerate if (compile-time flags)generate case (multi-configuration)Nested generate blocksGenerate-bound assertion checkers
10
SV LAB 10 โ File Handling & Memory Modeling
lab_file_memory.tar.gz
โถ
$fopen / $fclose$fdisplay / $fwrite$readmemh / $readmemb$writememh (memory dump)$fgets / $sscanf (line parsing)$fread / $fwrite (binary I/O)Behavioral RAM model classSelf-checking from golden filesCSV log generationECC memory model (Hamming code)
11
SV LAB 11 โ DPI-C Integration
lab_dpi.tar.gz
โถ
import/export "DPI-C" function/taskSV to C type mappingOutput/inout arguments (pointer passing)Fixed-size arrays across DPIchandle (opaque C pointer in SV)C reference model via chandlepure vs context DPI qualifierssvdpi.h typesShared library compilation (gcc -shared -fPIC)
12
SV LAB 12 โ Mini-UVM Testbench Integration
lab_mini_uvm.tar.gz
โถ
Base object class (MiniObject)Base component class (MiniComponent)Phase mechanism (build/connect/run/report)Transaction / sequence item designSequencer (mailbox-based arbitration)Driver (forever loop, handshake)Monitor (analysis broadcast via mailbox)Scoreboard (reference model + checker)Coverage collectorAgent (driver + monitor + sequencer)EnvironmentTest hierarchy (base/directed/random/stress)
LEVEL 1
SV Foundations for UVM
3 weeks ยท Delivered Inline (code + explanation)
1.1
Lab 1.1 โ OOP for Verification Engineers
DUT: None (pure SV OOP exercises)
โถ
BasePacket abstract class hierarchyEthPacket and AXIPacket concrete classesBaseChecker (ExactChecker, FuzzyChecker)$cast for runtime type checkingDeep copy problem in scoreboardsPolymorphism โ single scoreboard for multiple protocolsStatic members for transaction ID counting
1.2
Lab 1.2 โ Randomization for Constrained Stimulus
DUT: None (constraint exercises)
โถ
AXIRandTxn with full protocol constraint setdist weighted distribution for write/read biasImplication constraints for AXI burst rulessolve...before demonstrationpre_randomize / post_randomize hooksAdaptiveCoverageDriver: coverage-driven while loopInline constraint targeting for uncovered bins
1.3
Lab 1.3 โ IPC: Mailbox, Semaphore, Events for TB
DUT: None (IPC pattern exercises)
โถ
VerifEnvironment class with typed mailboxesBounded mailbox back-pressureSemaphore bus arbitration (2 masters, 1 bus)Event phase synchronisation (reset_done, gen_done, all_done)Fork-join_none with drain timeouttry_get() for clean shutdown detection
LEVEL 2
Basic UVM Concepts
4 weeks ยท Complete FILE PACKAGES (.tar.gz with all RTL, TB, scripts)
2.1
Lab 2.1 โ First Complete UVM Testbench (Counter DUT)
type_id::create() vs direct new()set_type_override() โ ALL instances replacedset_inst_override() โ ONE specific path replacedfactory.print() โ debug override tableOverride must be registered BEFORE super.build_phase()config_db path patterns (wildcard vs exact)Path specificity precedenceSetting int, bit, virtual interface typesvoid'() for optional get() / Fatal for mandatory get()
2.3
Lab 2.3 โ UVM Phasing Deep Dive
STATUS: INLINE (code + explanation)
โถ
Full phase sequence: build โ connect โ start_of_simulation โ run โ extract โ check โ report โ finalWhy build_phase is a function (zero time, top-down)Why run_phase is a task (consumes time, all parallel)raise_objection / drop_objection mechanismObjection trace debugging (+UVM_OBJECTION_TRACE)phase_demo_component showing all phase methods
uvm_analysis_port: 1-to-N non-blocking broadcastuvm_tlm_analysis_fifo: buffered, decoupled scoreboarduvm_subscriber: simplest subscriber base classuvm_analysis_imp: alternative for multi-port consumersWhy TLM over mailbox (decoupling, zero coupling)Adding 4th subscriber with ZERO changes to monitor/scoreboardMonitor thread vs scoreboard thread independence
Complete handshake sequence diagramsequence โ start_item โ grant โ finish_item โ blocked โ driver โ get_next_item โ drive โ item_done โ unblockWhy start_item grants arbitrationWhy finish_item BLOCKS until item_doneResponse data: driver populates item before item_donePipelined driver: double-buffer patternget_next_item vs get() distinctionDeadlock causes and detection
LEVEL 4
Advanced UVM
4 weeks ยท Delivered Inline with full code
4.1
Lab 4.1 โ Virtual Sequences & Virtual Sequencer
DUT: System with AXI master + APB slave ยท STATUS: INLINE
โถ
system_virtual_seqr (holds handles to AXI and APB sequencers)system_reset_sequence (coordinates both agents with fork/join)$cast from m_sequencer to virtual sequencer typeseq.start(p_seqr.axi_seqr) โ targeting specific sequencerFork-join for parallel multi-agent stimulussystem_env connecting virtual sequencer to real sequencersWhen to use virtual sequences vs layered sequences
4.2
Lab 4.2 โ UVM Register Abstraction Layer (RAL)
DUT: Memory controller with 4 config registers ยท STATUS: INLINE
โถ
ctrl_reg extends uvm_reguvm_reg_field (enable, mode, burst_len)field.configure() (size, offset, access type, reset value)mem_ctrl_reg_block extends uvm_reg_blockcreate_map() / add_reg() with addresseslock_model()axi_reg_adapter: reg2bus() and bus2reg()Register test: write() / read() / mirror()UVM_CHECK with mirror for post-reset verificationWhy RAL (protocol-agnostic test reuse)
LEVEL 5โ6
Protocol Verification & Full Industry-Style Projects
4 weeks each ยท Inline with full code
5.1
Lab 5.1 โ FIFO Verification Environment
DUT: Synchronous FIFO ยท STATUS: INLINE
โถ
Full verification plan (8 features โ sequences)fifo_seq_item with push/pop stimulus & response fieldsScoreboard reference model using SV queuecheck_field() per-flag comparisonpush-when-full & pop-when-empty scoreboard handlingOverflow/underflow sequence targeting
5.2
Lab 5.2 โ APB Slave Verification VIP
DUT: APB slave ยท STATUS: INLINE
โถ
apb_protocol_checker module with 6 SVA propertiesp_penable_after_psel / p_psel_stable_during_transferp_paddr_stable / p_pwdata_stable / p_no_x_prdatap_pready_timeout (##[0:16])bind statement for checker binding (no DUT modification)Protocol assertion coverage
AXI master VIP (active)DRAM model (behavioral)System scoreboardPerformance monitor (throughput + latency)Protocol checker (per-port AXI assertions)Coverage: M x S routing crossData integrity (write-read-compare)In-order completion verificationError handling (illegal address, ECC, timeout)Performance measurement under load
LEVEL 7โ8
Debugging, Optimization & Interview Preparation
2 weeks each ยท Delivered Inline
7.1
Lab 7.1 โ UVM Debugging Toolkit
STATUS: INLINE
โถ
UVM debugging decision tree (flowchart)uvm_topology_printer class (print_all)TLM connectivity checker (ap.size() == 0 warning)objection_tracker::dump_objections()Sequencer-driver deadlock watchdog timer+UVM_CONFIG_DB_TRACE / +UVM_VERBOSITY=UVM_HIGH
Common bugs with root cause & fix
Simulation ends at time 0 (missing raise_objection)Component not found in factory (missing utils macro)Analysis port silent failure (ap.size() == 0)Config_db type mismatchSequencer-driver deadlockPhase synchronisation issues
VIP reusability decision framework (active/passive/scoreboard)Top 50 UVM interview questions with detailed answersuvm_component_utils purposebuild_phase function vs run_phase taskComplete sequencer-driver handshakeuvm_do vs uvm_send vs uvm_rand_sendAnalysis port vs blocking portFactory internals (registry + override table)Passive agent use casesVirtual sequencer designType override vs instance overrideConfig_db path hierarchyWhat $cast returns on failureOverriding sequence items via factoryConfig_db::get() returning false
// System Modelling Curriculum
SystemC ยท RISC-V Architecture ยท GPU Design
9 Modules ยท 32 Weeks ยท 3 Complete System Projects
MODULE 1โ2
SystemC Foundation โ Modules, Concurrency & Data Types
Weeks 1โ6 ยท Hands-on labs with waveform simulation
Weeks 25โ28 ยท Simplified SM model, performance counters
โถ
Simplified SM module in SystemCWarp state machine (fetch / decode / issue / execute / writeback)Instruction buffer & dispatch queueOperand collector modelExecution unit models (ALU, FP, SFU)Shared memory model (banked SRAM)L1 cache model (direct-mapped / set-assoc)Interconnect crossbar modelMemory controller TLM modelPerformance counter instrumentationIPC (instructions per cycle) measurementOccupancy analysisBandwidth utilisation trackingCompute-bound vs memory-bound identificationKernel launch & grid simulation
M9
Capstone: RISC-V + GPU Heterogeneous SoC in SystemC TLM
Weeks 29โ32 ยท Full system integration project
โถ
RISC-V RV32IM host CPU modelSimplified GPU accelerator model (4 warps, 8 threads)AXI TLM-2.0 system interconnectDMA engine for CPU โ GPU data transferKernel command queue (doorbell register)Shared memory pool (host + device visible)Interrupt-driven kernel completionBare-metal driver software in CMatrix multiply kernel on GPU modelEnd-to-end performance simulationArchitecture trade-off report (number of SMs vs latency)Portfolio-ready project on Git
Semiconductor Linux workflows · User/group management
►
Linux architecture & shell environmentSemiconductor Linux workflowsUser & group managementpwd / ls / cdmkdir / rm / cp / mvtouch / treeSymbolic linkschmodchownUser/group access control
Weeks 10โ15 · Cadence Innovus · Die sizing โ macro placement โ power grid design
3.1
Floorplan Initialization & Die Sizing
Core area, aspect ratio, utilization, IO ring
►
Die area & core area calculationAspect ratio selectionCore utilization target (70โ80%)IO pad placement & ring planningCorner cells & filler cellsRectilinear floorplansBlockages (hard, soft, partial)Halos around macrosChip-level vs block-level floorplanningFloorplan quality metrics (HPWL, congestion)
3.2
Macro Placement & Pin Assignment
Memory/IP placement, channel routing, data flow orientation
►
Macro placement objectives (data flow, timing, area)Memory compiler orientation & abutmentAnalog/mixed-signal IP placementChannel routing between macrosMacro-to-macro spacing rulesPin assignment โ primary input/output locationsBus grouping & bit orderingFeedthrough planningPartition-level interface planningLab: Full floorplan with 4 memory macros โ timing-aware
3.3
Power Planning & Power Grid Design
VDD/VSS rings, straps, mesh, power rails โ IR drop budgeting
►
Power domain definition (VDD, VSS, VDDIO)Power ring sizing & placementPower strap width & pitch calculationPower mesh topology (H-tree, grid, star)Standard cell rail (VDD/VSS rows)Follow-pin connectionsIR drop budget (static & dynamic)Electromigration (EM) current density limitsPower domain isolation cellsUPF-driven multi-voltage floorplanDecap cell insertion strategyLab: Power grid design with Cadence Voltus IR analysis
Global routing (GR) โ resource allocationTrack assignmentDetail routing โ via optimizationNDR routing rules for critical netsClock net routing (shielding, NDR)Signal integrity โ crosstalk noise analysisAntenna rule violations & fixesRouting DRC fixing (spacing, short, open)Via doubling / via ladderingMetal fill insertionFiller cell insertionLab: Full routing run โ DRC-clean with congestion analysis
5.2
Static Timing Analysis (STA) โ Full Signoff
Cadence Tempus โ setup/hold, MCMM, ECO flow
►
STA fundamentals โ timing paths (data, clock)Setup time & hold time equationsSlack calculation (WNS / TNS / NVP)Clock domain crossing timing (async paths)CPPR โ Common Path Pessimism RemovalParasitic extraction โ SPEF, RC cornersPVT corners (process: SS/FF/TT, voltage, temp)MMMC analysis โ all corners simultaneouslySignoff ECO โ fixing violations at layout levelreport_timing โ path analysis & debugreport_constraint โ exceptions validationFalse path & multicycle path validationLab: Full STA signoff with Cadence Tempus โ MCMM closure
5.3
Power Analysis & IR Drop / EM Signoff
Cadence Voltus โ static & dynamic IR, electromigration
►
Static power analysis โ leakage currentDynamic power analysis โ switching activityVCD / SAIF activity annotationStatic IR drop analysisDynamic IR drop analysisIR drop hotspot identification & fixingElectromigration (EM) โ average & RMS currentEM violation fixing โ metal width upsizingPower grid strengtheningDecap insertion for dynamic IRPower budget reportingLab: IR drop & EM analysis with Cadence Voltus
5.4
Signal Integrity & Crosstalk Analysis
Noise-on-delay, glitch analysis, SI-aware routing
►
Capacitive coupling & crosstalk mechanismsNoise-on-delay (pessimistic / optimistic)Glitch noise analysis (SI-threshold)Victim / aggressor net identificationSI-aware CTS fixingShielding critical nets (VDD/VSS guards)Wire spacing increase for SI fixBuffer insertion for noise immunitySI timing signoff with SPEF parasitics
PHASE 6
Physical Verification & GDSII Tapeout Signoff
Weeks 27โ32 · Cadence Calibre · DRC โ LVS โ ERC โ antenna โ metal fill โ GDSII
Electrical rule checks, antenna violations, foundry fill requirements
►
ERC โ floating gate detectionERC โ power/ground short detectionAntenna effect mechanism (gate oxide damage)Antenna ratio calculation (metal/via area)Antenna violation fixing (jumper via, antenna diode)Metal density requirements per layerAutomated metal fill insertion (dummy fill)Metal fill impact on timing (parasitic)Via maximization for reliabilityCMP (Chemical Mechanical Planarization) density rules
6.4
GDSII Tapeout & Signoff Checklist
Final tapeout flow โ GDSII streaming, layer map, sign-off checklist
►
GDSII stream out (Virtuoso / Innovus)Layer map file preparationTop-level GDSII merge (chip + IP + IO)GDSII validation (Calibre DRC final run)LVS final run on merged GDSIISTA final signoff โ all PVT corners cleanIR drop final signoff โ all domains cleanEM final signoffTapeout checklist (100-point verification)Foundry PDK submission packageLab: End-to-end mini chip tapeout โ GDSII to foundry format
6.5
ECO (Engineering Change Order) Flow
Post-mask ECO, functional ECO, metal-only ECO
►
Functional ECO โ logic change implementationTiming ECO โ setup/hold fix at layoutMetal-only ECO โ no new diffusion masksSpare cell methodologyECO cell placement constraintsIncremental routing after ECOECO verification (LVS / DRC re-check)Formal verification of ECO correctnessPost-ECO STA sign-off